FPGA Implementation of Vehicle Emission Monitoring and Alert System

Abstract

This paper presents the design, synthesis, and full hardware validation of a real-time vehicle emission monitoring and alert system implemented in Verilog HDL on a Xilinx Artix-7 FPGA (XC7A100TCSG324-1) using the Arty A7-35T development board. The system simultaneously monitors four critical vehicular pollutants — Carbon Monoxide (CO), Carbon Dioxide (CO2), Sulfur Dioxide (SO2), and Particulate Matter (PM2.5) — by processing 10-bit Analog-to-Digital Converter (ADC) in-puts through a fully synthesisable fixed-point arithmetic pipeline. Pollutant thresholds are aligned with WHO Air Quality Guidelines and Bharat Stage 6 (BS6) emission norms: CO at 20%, CO2 at 15%, SO2 at 10%, and PM2.5 at 100 μg/m3. When any threshold is exceeded, a threshold com-parison flag is asserted within a single clock cycle (10 ns at 100 MHz), and a ―Needs Repair‖ alert is displayed on a 16×2 LCD with rotating multi-gas messages. End-to-end alert latency — from ADC value presentation to LCD character update — is analytically derived and experimentally confirmed to be no greater than 30 clock cycles, or 300 ns at 100 MHz, which is more than four orders of magnitude faster than comparable IoT-based SMS alert systems (10–20 seconds). Post-implementation results show a total on-chip power consumption of 0.077 W, 9.86% LUT utilisation, 6.69% flip-flop utilisation, and a worst-case timing slack of +0.1 ns. Hardware validation is performed using the Vivado Integrated Logic Analyser (ILA) for internal waveform capture and the Virtual In-put/Output (VIO) core for real-time ADC stimulus injection. The prototype establishes a scalable, low-power, connectivity-independent plat-form for automotive emission diagnostics and sets the stage for physical sensor integration (MQ-7, MQ-135, MQ-136, PMS7003), IoT connectivity, and on-chip machine learning inference.