A Comprehensive Review of FPGA-Based power Efficient Arithmetic Logic Units using Carry-save Arithmetic synthesis, analysis and comparative Insights

Abstract

The unremitting requirement on high-performance and energy-efficient computing in embedded systems, digital signal processing (DSP), and cryptographic applications has fuelled the need of optimized Arithmetic Logic Unit (ALUs). Field-Programmable Gate Arrays (FPGAs) provide a programmable platform that is suitable to deploy application specific ALU structure. Carry-Save Arithmetic (CSA) of various optimization approaches has become one of the key approaches to optimizing the speed and power usage of arithmetic circuits, especially in multiple-operand operations such as accumulation and multiplication. In this paper, the authors provide a review of the power-efficient ALU designs that are based on carry-save arithmetic and use FPGA. We perform an analytical methodology of synthesis methodologies, architecture variants and optimization strategies that have been used to include CSA in the ALU datapaths. An in-depth analysis of power, performance and area (PPA) trade-offs with particular attention to dynamic reduction of power by minimizing glitching and critical path delays is discussed in the review. Moreover, we provide comparative data about modern-day designs, comparing them to traditional binary arithmetic designs in the throughput, latency, logic usage, and on-chip power dissipation. Important issues like design complexity, verification costs and how to interface CSA units with standard logic are addressed extremely. Lastly, the paper provides a note of future research, such as the synergy between CSA and approximate computing, CSA use as a low-voltage operation in FPGAs, and CSA-based datapath generation using automated high-level synthesis tools. The goal of this survey is to be a reference point to a researcher and engineer as they think of the next generation of power-constrained, and yet, arithmetic systems on reconfigurable hardware.