Performance Enhancement of Optimized Dynamic Circuit for Low-Power and High- Speed Applications

Abstract

In this work the design of a high-speed, low-power dynamic comparator for analog-to-digital converter (ADC) applications is proposed and analyzed. The design incorporates a differential amplifier-based pre-amplifier and a regenerative latch made up the two-stage design of the proposed circuit. In order to improve performance, more transistors are added to act as control switches, isolating the pre-amplifier stage once the latch is engaged. Without compromising comparison accuracy, this method significantly lowers kickback noise and dynamic power dissipation. To achieve a power-delay trade-off, an improved version of the proposed design is also developed, offering flexibility for various design objectives. The Cadence Virtuoso tool is used to construct and simulate the comparator in 45nm CMOS technology. The proposed circuits key parameters such as the power consumption, offset voltage, propagation delay, and power-delay product and offset voltage for which the simulation results are significantly superior to those of conventional dynamic comparators. Because of its enhanced speed and energy efficiency, the recommended comparator is perfect for high-performance, battery-operated, low- voltage ADC systems