Design, Validation and Characterization Grain-128 AEADv2 Lightweight Crypto IP Core

Abstract

The need for low resource devices has significantly increased as a result of the development of Internet-of-things ap-plications. Various light weighted stream cipher algorithms have emerged as promising solutions for securing IoT communica-tions. They are used on hardware because of its simplicity, speed, limited resources and processing power. Lightweight crypto-graphy overcomes these constraints by optimum utilization of the resources available, while maintaining security, Because of their economical implementations, Grain128AEAD ciphers stand out among other stream ciphers. There are different variants of the Grain cipher, and Grain-128AEADv2 is one of the ciphers. Grain 128 AEADv2cipher with 64 bits plaintext and 128 bits key 96 bit nonce(IV),64 bits associated data forming a 64 bits ciphertext and 64 bits Tag. The Grain 128AEAD cipher is small and quite efficient. In this paper, Design validation and characterization of grain128AEADv2 cipher IP core. The hardware platform used the Xilinx Artix-7 FPGA board and Vivado is used for simulations, synthesis, and implementations utilizing the Verilog hardware description language. The performance parameters results were observed with the help of Xilinx Vivado.