Design and comparative analysis of low power, area efficient optimized 10T Hybrid full adder for high performance Arithmetic and Logic Unit
In this time of rapid invention and utilisation of battery-operated products, battery life is a significant problem. Because the traditional Full Adder(FA) uses more energy, we used low power FA circuitry in this study and examined how it functions in lieu of the traditional Full Adder circuitry. The presented design of FA consumes low power, requires lesser no. of transistors and is area efficient compared to existing design.