FPGA Implementation of A 64-Tap Fir Filter Using Radix-8 Booth Multiplier In Verilog

Abstract

In this paper, the FPGA implementation of a 64-tap FIR filter is realized by using a Radix-8 Booth multiplier for efficient multiplication and high-speed performance. Designed using Verilog HDL, and implemented on a Xilinx Artix-7 FPGA (xc7a100tcsg324-1), the prototype was implemented on a Nexys A7-100T development board, with synthesis and implementation performed in Vivado 2021.2. Considering the computational accuracy and hardware complexity, the Q1.15 fixed-point format is adopted in this design. In this work, the architecture is analyzed based on the resource utilization and operating frequency, making it appropriate for real-time FPGA-based digital signal processing applications.