FPGA Implementation and Synthesis of Rate-1/2 Convolutional Encoder and Deterministic Viterbi Decoder on Basys3 (Artix-7)

Abstract

Robust forward error correction (FEC) techniques are necessary for reliable data transmission in noisy communication channels. Because of its simplicity, deterministic behavior, and suitability for digital circuits, convolutional encoding in conjunction with Viterbi decoding has long been recognized as one of the most effective error-correcting schemes for real-time hardware environments. This study uses Verilog HDL to present the full design, simulation, hardware implementation, and experimental validation of a rate 1/2 convolutional encoder coupled with a deterministic Viterbi decoder. The Basys3 Artix-7 FPGA development board is used to implement both encoder and decoder architectures. The decoder uses state transitions and branch metric comparison to implement the Viterbi algorithm, while the convolutional encoder uses a two-bit shift-register- based state machine that generates two parity bits for each input bit. The accuracy and robustness of the implemented design are confirmed by the entire system, which includes simulation on Vivado, testbench-based random bitstream testing, and real-time FPGA verification. Because of its resource efficiency, the suggested design can be used for low-power embedded hardware, digital communication system prototypes, and academic learning. Advanced FEC schemes like turbo codes, LDPC codes, soft-decision Viterbi decoders, and SDR-based implementations use the work as an experimental basis.